{"title":"综合业务接入网622mbps ATM OAM功能设计","authors":"Sang Ho Lee","doi":"10.1109/ICC.1998.683057","DOIUrl":null,"url":null,"abstract":"As the various types of application services are increased in the ATM (asynchronous transfer mode) network, it becomes a very important requirement for the ATM network equipment to provide for a higher transfer rate and to detect network failure or service degradation. In order to meet these requirements we develop a monolithic single chip device which can handle VPI/VCI address translation, cell appending, counting, and OAM (operation and management) processing for 65,536 VCs (virtual circuits) in real time. This paper describes the architectural design of a 622 Mbps ATM layer ASIC (application specific integrated circuit) which is under development. This ASIC is applicable for developing network equipment in B-ISDN. This supports both the NNI (network-network interface) and the UNI (user-network interface) and has ITU-TS based F4 or F5 level OAM function processing in real time. Also this chip can measure QoS (quality of service) and network parameters related to such OAM functions.","PeriodicalId":218354,"journal":{"name":"ICC '98. 1998 IEEE International Conference on Communications. Conference Record. Affiliated with SUPERCOMM'98 (Cat. No.98CH36220)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of 622 Mbps ATM OAM functions for the integrated service access network\",\"authors\":\"Sang Ho Lee\",\"doi\":\"10.1109/ICC.1998.683057\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As the various types of application services are increased in the ATM (asynchronous transfer mode) network, it becomes a very important requirement for the ATM network equipment to provide for a higher transfer rate and to detect network failure or service degradation. In order to meet these requirements we develop a monolithic single chip device which can handle VPI/VCI address translation, cell appending, counting, and OAM (operation and management) processing for 65,536 VCs (virtual circuits) in real time. This paper describes the architectural design of a 622 Mbps ATM layer ASIC (application specific integrated circuit) which is under development. This ASIC is applicable for developing network equipment in B-ISDN. This supports both the NNI (network-network interface) and the UNI (user-network interface) and has ITU-TS based F4 or F5 level OAM function processing in real time. Also this chip can measure QoS (quality of service) and network parameters related to such OAM functions.\",\"PeriodicalId\":218354,\"journal\":{\"name\":\"ICC '98. 1998 IEEE International Conference on Communications. Conference Record. Affiliated with SUPERCOMM'98 (Cat. No.98CH36220)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-06-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICC '98. 1998 IEEE International Conference on Communications. Conference Record. Affiliated with SUPERCOMM'98 (Cat. No.98CH36220)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICC.1998.683057\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICC '98. 1998 IEEE International Conference on Communications. Conference Record. Affiliated with SUPERCOMM'98 (Cat. No.98CH36220)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICC.1998.683057","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of 622 Mbps ATM OAM functions for the integrated service access network
As the various types of application services are increased in the ATM (asynchronous transfer mode) network, it becomes a very important requirement for the ATM network equipment to provide for a higher transfer rate and to detect network failure or service degradation. In order to meet these requirements we develop a monolithic single chip device which can handle VPI/VCI address translation, cell appending, counting, and OAM (operation and management) processing for 65,536 VCs (virtual circuits) in real time. This paper describes the architectural design of a 622 Mbps ATM layer ASIC (application specific integrated circuit) which is under development. This ASIC is applicable for developing network equipment in B-ISDN. This supports both the NNI (network-network interface) and the UNI (user-network interface) and has ITU-TS based F4 or F5 level OAM function processing in real time. Also this chip can measure QoS (quality of service) and network parameters related to such OAM functions.