采用 3D sequential CoolCube™ 14 纳米技术的高密度 SRAM 位元结构

2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI:10.1109/S3S.2016.7804376

M. Brocard, R. Boumchedda, J. Noel, K. Akyel, B. Giraud, E. Beigné, D. Turgis, S. Thuries, G. Berhault, O. Billoint

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引用次数: 11

摘要

本文介绍了采用基于 FD-SOI 晶体管的三维连续 CoolCube™ 技术设计的 14nm 节点高密度 4T SRAM 位元组。通过布局后仿真，使用内部 SPICE 特性测试平台优化了 4T SRAM 位元组的关键操作（读取和保持）。结果表明，与采用 14 纳米 FD-SOI 技术的平面 6T SRAM 位元组相比，拟议的 3D 4T 位元组可减少 30% 的占位面积。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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High density SRAM bitcell architecture in 3D sequential CoolCube™ 14nm technology

In this paper, we present a high density 4T SRAM bitcell designed with 3D sequential CoolCube™ technology based on FD-SOI transistors in 14nm node. An in-house SPICE characterization testbench is used to optimize the critical operations (read and hold) of a 4T SRAM bitcell through post layout simulations. Results show that the proposed 3D 4T Bitcell offers 30% footprint reduction compared to the planar 6T SRAM bitcell in 14nm FD-SOI technology.

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来源期刊

2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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