M. Minami, N. Ohki, H. Ishida, T. Yamanaka, K. Ishibashi, A. Shimizu, T. Kure, T. Nishida, T. Nagano
{"title":"采用6.93-/spl mu/m/sup 2/ n栅全CMOS SRAM单元技术，外围电路采用高性能1.8 v双栅CMOS","authors":"M. Minami, N. Ohki, H. Ishida, T. Yamanaka, K. Ishibashi, A. Shimizu, T. Kure, T. Nishida, T. Nagano","doi":"10.1109/VLSIT.1995.520836","DOIUrl":null,"url":null,"abstract":"A high-performance microprocessor-compatible small size full CMOS SRAM cell technology has been developed. A 0.3-/spl mu/m gate length load pMOSFET, formed utilizing amorphous-Si-film through-channel implantation, is merged with a 0.25-/spl mu/m gate length pMOSFET for the peripheral circuits. Mask-free contact for TiN local interconnect is developed with wet etching. A 6.93-/spl mu/m/sup 2/ cell area and a high-performance 1.8-V circuit are thus realized.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 6.93-/spl mu/m/sup 2/ n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuits\",\"authors\":\"M. Minami, N. Ohki, H. Ishida, T. Yamanaka, K. Ishibashi, A. Shimizu, T. Kure, T. Nishida, T. Nagano\",\"doi\":\"10.1109/VLSIT.1995.520836\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high-performance microprocessor-compatible small size full CMOS SRAM cell technology has been developed. A 0.3-/spl mu/m gate length load pMOSFET, formed utilizing amorphous-Si-film through-channel implantation, is merged with a 0.25-/spl mu/m gate length pMOSFET for the peripheral circuits. Mask-free contact for TiN local interconnect is developed with wet etching. A 6.93-/spl mu/m/sup 2/ cell area and a high-performance 1.8-V circuit are thus realized.\",\"PeriodicalId\":328379,\"journal\":{\"name\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1995.520836\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 Symposium on VLSI Technology. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1995.520836","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 6.93-/spl mu/m/sup 2/ n-gate full CMOS SRAM cell technology with high-performance 1.8-V dual-gate CMOS for peripheral circuits
A high-performance microprocessor-compatible small size full CMOS SRAM cell technology has been developed. A 0.3-/spl mu/m gate length load pMOSFET, formed utilizing amorphous-Si-film through-channel implantation, is merged with a 0.25-/spl mu/m gate length pMOSFET for the peripheral circuits. Mask-free contact for TiN local interconnect is developed with wet etching. A 6.93-/spl mu/m/sup 2/ cell area and a high-performance 1.8-V circuit are thus realized.
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