Sub-30nm Mosfet Fabrication Technology Incorporating Precise Dopant Profile Design using Diffusion-Less High-Activation Laser Annealing

Sub-30nm MOSFET fabrication technology is proposed based on a dedicated process redesign suitable for a non-melt laser annealing technique. Two major features of the laser annealing (LA), i.e. diffusion-less and higher dopant activation enable us to apply more elaborate channel engineering, involving multiple halo implantations and optimized gate-predoping, that contributes further scaling of a functional gate-length (Lg) and effective gate-insulator thickness (Tinv), maintaining sufficient current drivability prior to any local stress engineering applied, for instance, ION = 650/340 [muA/mum] (nMOS/pMOS) at IOFF = 100 nA/mum, Vdd = 0.9V, were obtained for sub-30nm Lg (and also sidewall length) devices