{"title":"集成电路布局和可制造性:关键环节和设计流程的影响","authors":"A. Kahng","doi":"10.1109/ICVD.1999.745132","DOIUrl":null,"url":null,"abstract":"We assess the prospects for new tools and flows in the interface between layout design and manufacturability. We begin with a review of classic elements of this interface, then focus on more recently critical issues: (i) layout design for reduced CMP variability; (ii) layout design for PSM; and (iii) layout design for OPC. Our discussion highlights the many ways in which layout affords effective means of optimizing manufacturability, as well as opportunities for research and development.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"IC layout and manufacturability: critical links and design flow implications\",\"authors\":\"A. Kahng\",\"doi\":\"10.1109/ICVD.1999.745132\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We assess the prospects for new tools and flows in the interface between layout design and manufacturability. We begin with a review of classic elements of this interface, then focus on more recently critical issues: (i) layout design for reduced CMP variability; (ii) layout design for PSM; and (iii) layout design for OPC. Our discussion highlights the many ways in which layout affords effective means of optimizing manufacturability, as well as opportunities for research and development.\",\"PeriodicalId\":443373,\"journal\":{\"name\":\"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-01-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVD.1999.745132\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.1999.745132","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
IC layout and manufacturability: critical links and design flow implications
We assess the prospects for new tools and flows in the interface between layout design and manufacturability. We begin with a review of classic elements of this interface, then focus on more recently critical issues: (i) layout design for reduced CMP variability; (ii) layout design for PSM; and (iii) layout design for OPC. Our discussion highlights the many ways in which layout affords effective means of optimizing manufacturability, as well as opportunities for research and development.