Investigation of high-k HfN multilayer gate dielectrics for MISFET fabricated with Si surface flattening

In this paper, we have investigated MISFETs with HfNxmultilayer gate dielectrics fabricated with Si surface flattening process. The ID- VGcharacteristics of fabricated MISFETs with 2- and 4-layer gate dielectrics showed negligible hysteresis and excellent subthreshold swing (SS) of 71.6 and 72.5 mV/dec., respectively. This is attributed of Si surface flattening process. Furthermore, although the thickness of gate dielectrics was increased by increasing the number of dielectric layers, the extracted equivalent oxide thickness (EOT) showed similar value. Furthermore, the on/off current (Ion/Ioff) ratio was increased by one order of magnitude.