{"title":"在减小-1模2N+1熔接乘加单元上","authors":"C. Efstathiou, I. Voyiatzis","doi":"10.1109/DTIS.2011.5941427","DOIUrl":null,"url":null,"abstract":"In this work the most efficient modulo 2<sup>n</sup>+1 multiplication algorithm for diminished-1 operands proposed to date is extended to compute expressions of the form |A×B + D|<inf>2n+1</inf>. The derived partial products are reduced by a carry save adder tree to two operands, which are finally added by a modulo 2<sup>n</sup>+1 adder. The proposed architecture can find applicability in systems in which fused multiply-add units can accelerate the execution of the targeting algorithms, for example digital signal processing and cryptography systems.","PeriodicalId":409387,"journal":{"name":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"On the diminished-1 modulo 2N+1 fused multiply-add units\",\"authors\":\"C. Efstathiou, I. Voyiatzis\",\"doi\":\"10.1109/DTIS.2011.5941427\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work the most efficient modulo 2<sup>n</sup>+1 multiplication algorithm for diminished-1 operands proposed to date is extended to compute expressions of the form |A×B + D|<inf>2n+1</inf>. The derived partial products are reduced by a carry save adder tree to two operands, which are finally added by a modulo 2<sup>n</sup>+1 adder. The proposed architecture can find applicability in systems in which fused multiply-add units can accelerate the execution of the targeting algorithms, for example digital signal processing and cryptography systems.\",\"PeriodicalId\":409387,\"journal\":{\"name\":\"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DTIS.2011.5941427\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTIS.2011.5941427","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On the diminished-1 modulo 2N+1 fused multiply-add units
In this work the most efficient modulo 2n+1 multiplication algorithm for diminished-1 operands proposed to date is extended to compute expressions of the form |A×B + D|2n+1. The derived partial products are reduced by a carry save adder tree to two operands, which are finally added by a modulo 2n+1 adder. The proposed architecture can find applicability in systems in which fused multiply-add units can accelerate the execution of the targeting algorithms, for example digital signal processing and cryptography systems.