浮点除法和平方根算法及其在AMD-K7/sup TM/微处理器上的实现

S. Oberman
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引用次数: 141

摘要

本文介绍了符合IEEE 754和/spl times/87标准的AMD-K7浮点除法和平方根算法及其实现。AMD-K7处理器采用级数展开的迭代实现,以二次收敛于商和平方根。高度精确的初始近似和高性能共享浮点乘法器有助于在高工作频率下实现低除法和平方根延迟。一种新的分时技术允许在除法或平方根计算进行时进行独立的浮点乘法运算。所有舍入模式和目标精度的精确IEEE 754舍入已经通过常规的定向和随机测试程序进行了验证,并使用ACL2定理证明器进行了机械检查的形式化证明。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Floating point division and square root algorithms and implementation in the AMD-K7/sup TM/ microprocessor
This paper presents the AMD-K7 IEEE 754 and /spl times/87 compliant floating point division and square root algorithms and implementation. The AMD-K7 processor employs an iterative implementation of a series expansion to converge quadratically to the quotient and square root. Highly accurate initial approximations and a high performance shared floating point multiplier assist in achieving low division and square root latencies at high operating frequencies. A novel time-sharing technique allows independent floating point multiplication operations to proceed while division or square root computation is in progress. Exact IEEE 754 rounding for all rounding modes and target precisions has been verified by conventional directed and random testing procedures, along with the formulation of a mechanically-checked formal proof using the ACL2 theorem prover.
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