集成1-2.5 Gbps低抖动CMOS收发器，内置自检功能

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI:10.1109/VLSIC.1999.797230

Ah-Lyan Yee, R. Gu, Heng-Chih-Lin, A. Tsong, R. Prentice, J. Tran, R. Venett, S. Spencer, V. Pathak, E. Suder, M. Izzard

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引用次数: 5

摘要

本文介绍了一种高速、低抖动的CMOS收发器，该收发器具有10对1全双工串行反序列化功能、时钟恢复、高速差分I/O和内置自检(BIST)功能。它的制造和测试工作在宽频率范围(1至2.5 Gbps)，低抖动和低功率(76 ps P-P, 500 mW @ 2.5 Gbps)。它被设计为ASIC标准单元库的一个组成部分，并被实现为独立设计以及具有32个收发器的大型设计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An integratable 1-2.5 Gbps low jitter CMOS transceiver with built in self test capability

This paper describes a high speed, low jitter CMOS transceiver, which includes 10 to 1 full duplex serialize-deserialize function, clock recovery, high speed differential I/O, and Built In Self Test (BIST). It was fabricated and tested to work at wide frequency range (1 to 2.5 Gbps) with low jitter and low power (76 ps P-P, 500 mW @ 2.5 Gbps). It was designed to be a component of ASIC standard cell library and was implemented as a stand alone design as well as in a large design with 32 transceivers.

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来源期刊

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

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