Analysis of the impact of metastability phenomenon on the latency and power consumption of synchronizer circuits

In modern System on Chips (SoCs) different blocks may use clock signals with different frequencies, in which case SoC is said to have multiple clock domains. The signal that travels from one clock domain to another needs to be synchronized in the receiving domain to prevent occurrence of metastability phenomenon, i.e. a degradation of a signal. Synchronization is implemented by so called synchronizing devices, which are a set of flip-flops in a certain configuration. This paper researches timing characteristics and power consumption of different types of synchronizers by using elements from SAED32/28nm Educational Design Kit (EDK).