等效电容引导假体填充插入的时序和可制造性

Sheng-Jung Yu, Chen-Chien Kao, Chia‐Han Huang, I. Jiang
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引用次数: 4

摘要

为了提高加工工艺性,为减少化学机械抛光后的厚度变化,普遍采用假体填充法。然而,插入的金属填充物会引起对附近信号网的显著耦合,从而可能导致时序退化。现有的时间感知填充插入策略侧重于优化感应耦合电容,而不是优化产生的等效电容。因此,无法完全捕捉到对时间的影响。相反,本文分析了虚拟填充的等效电容友好区。该分析可以明智地指导虚拟填充的插入,以防止定时临界网的等效电容产生不必要的增加。基于ICCAD 2018 CAD竞赛基准套件的实验结果表明,我们的解决方案优于竞赛获胜团队和最先进的工作。此外,我们的分析结果与实际等效电容值高度相关,确实为时序感知的假填充插入提供了准确的指导。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability
To improve manufacturability, dummy fill insertion is widely adopted for reducing the thickness variation after chemical mechanical polishing. However, inserted metal fills induce significant coupling to nearby signal nets, thus possibly incurring timing degradation. Existing timing-aware fill insertion strategies focus on optimizing induced coupling capacitance instead of resultant equivalent capacitance. Therefore, the impact on timing cannot be fully captured. In contrast, in this paper, we analyze equivalent capacitance friendly regions for dummy fills. The analysis can wisely guide dummy fill insertion to prevent unwanted and unnecessary increase in the resultant equivalent capacitance of timing critical nets. Experimental results based on the ICCAD 2018 CAD Contest benchmark suite show that our solution outperforms the contest winning teams and state-of-the-art work. Moreover, our analysis results are highly correlated to actual equivalent capacitance values and indeed provide accurate guidance for timing-aware dummy fill insertion.
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