采用独立控制双栅器件的动态电路技术

2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI:10.1109/SOI.2005.1563539

J. B. Kuang, K. Kim, C. Chuang, H. Ngo, K. Nowka

{"title":"采用独立控制双栅器件的动态电路技术","authors":"J. B. Kuang, K. Kim, C. Chuang, H. Ngo, K. Nowka","doi":"10.1109/SOI.2005.1563539","DOIUrl":null,"url":null,"abstract":"In this paper, conditional keeper, charge sharing prevention, and clock load reduction techniques for symmetrical and asymmetrical DG devices have been presented. Performance benefit, noise immunity, area and power efficiency can be achieved when technology features are judiciously utilized in the design of dynamic circuits.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Dynamic circuit techniques using independently controlled double-gate devices\",\"authors\":\"J. B. Kuang, K. Kim, C. Chuang, H. Ngo, K. Nowka\",\"doi\":\"10.1109/SOI.2005.1563539\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, conditional keeper, charge sharing prevention, and clock load reduction techniques for symmetrical and asymmetrical DG devices have been presented. Performance benefit, noise immunity, area and power efficiency can be achieved when technology features are judiciously utilized in the design of dynamic circuits.\",\"PeriodicalId\":116606,\"journal\":{\"name\":\"2005 IEEE International SOI Conference Proceedings\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE International SOI Conference Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOI.2005.1563539\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International SOI Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.2005.1563539","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

本文介绍了对称和非对称DG器件的条件保持器、电荷共享预防和时钟负载降低技术。在动态电路的设计中合理地利用技术特点，可以实现性能效益、抗噪性、面积和功率效率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Dynamic circuit techniques using independently controlled double-gate devices

In this paper, conditional keeper, charge sharing prevention, and clock load reduction techniques for symmetrical and asymmetrical DG devices have been presented. Performance benefit, noise immunity, area and power efficiency can be achieved when technology features are judiciously utilized in the design of dynamic circuits.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2005 IEEE International SOI Conference Proceedings

自引率

0.00%

发文量