单端7T SRAM单元的回写技术

2017 IEEE 37th International Conference on Electronics and Nanotechnology (ELNANO) Pub Date : 2017-04-18 DOI:10.1109/ELNANO.2017.7939728

Vazgen Melikyan, A. Avetisyan, D. Babayan, Karo H. Safaryan, Tigran Hakhverdyan

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引用次数: 1

摘要

本文提出了一种新的Write-Back方案，该方案解决了7晶体管单端静态随机存储器(SE-SRAM)位元存储阵列的半选择操作问题，并且比传统的Write-Back技术更快。单元内的数据敏感且可能发生翻转，因此该方案在不降低性能的情况下改善了半选择单元的稳定性问题。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Write-back technique for single-ended 7T SRAM cell

This paper presents the new Write-Back scheme, which solve the half-select operation problem and faster than conventional Write-Back technique for memory array with seven-transistor (7T) single-ended static random access memory (SE-SRAM) bit cell. Data in the cells are sensitive and flipping can happen, so proposed scheme improves the stability issue for half-selected cells without performance degradation.

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来源期刊

2017 IEEE 37th International Conference on Electronics and Nanotechnology (ELNANO)

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