{"title":"5 nm栅极长度互补纳米线隧道晶体管的量子校正模拟","authors":"A. Heigl, G. Wachutka","doi":"10.1109/ASDAM.2008.4743294","DOIUrl":null,"url":null,"abstract":"Using numerical device simulation we investigated in detail the operational behavior of a cylindrical nanowire tunneling transistor (TFET) and the effect of quantum confinement on its characteristics, with a strong focus on the scalability of such devices. Among others, we discuss the potential device improvements by considering alternative materials for the gate-stack and the source region.","PeriodicalId":306699,"journal":{"name":"2008 International Conference on Advanced Semiconductor Devices and Microsystems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Quantum-Corrected Simulation of Complementary Nanowire Tunneling Transistors of 5 nm Gate-Length\",\"authors\":\"A. Heigl, G. Wachutka\",\"doi\":\"10.1109/ASDAM.2008.4743294\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Using numerical device simulation we investigated in detail the operational behavior of a cylindrical nanowire tunneling transistor (TFET) and the effect of quantum confinement on its characteristics, with a strong focus on the scalability of such devices. Among others, we discuss the potential device improvements by considering alternative materials for the gate-stack and the source region.\",\"PeriodicalId\":306699,\"journal\":{\"name\":\"2008 International Conference on Advanced Semiconductor Devices and Microsystems\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 International Conference on Advanced Semiconductor Devices and Microsystems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASDAM.2008.4743294\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International Conference on Advanced Semiconductor Devices and Microsystems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASDAM.2008.4743294","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Quantum-Corrected Simulation of Complementary Nanowire Tunneling Transistors of 5 nm Gate-Length
Using numerical device simulation we investigated in detail the operational behavior of a cylindrical nanowire tunneling transistor (TFET) and the effect of quantum confinement on its characteristics, with a strong focus on the scalability of such devices. Among others, we discuss the potential device improvements by considering alternative materials for the gate-stack and the source region.