Critical technology challenges in low power electronics

The availability of ULSI CMOS operating at 1 V can lead to several revolutionary applications. In addition to innovative circuit designs, new materials and processes need to be developed for low power electronics. This is due to the fact that power dissipation depends on parasitic capacitance. Critical technologies are high quality high and low K dielectric materials and appropriate metalization schemes. We have successfully used rapid isothermal processing (RIP) for the deposition of high K and low K dielectric materials. We have used RIP assisted metalorganic chemical vapor deposition (MOCVD) technique for the deposition of high K materials having very low leakage current density (<1 pA/cm/sup 2/ at 1 V). It has been found that even at low processing temperatures (300 to 400/spl deg/C) the residual stress of the materials processed by conventional furnaces is much higher than that can be obtained by RIP. From the manufacturing point of view, new equipments need to be developed for the successful implementation of new technologies. The objective of this paper is to present our recent materials and processing results and the possible directions in meeting the equipment and process integration challenges.