{"title":"MCM和ASEM设计中基于产量的系统划分策略","authors":"S. Khan, V. Madisetti","doi":"10.1109/MCMC.1994.292512","DOIUrl":null,"url":null,"abstract":"We propose a new quantitative approach to MCM and ASEM system partitioning under yield, I/O, and area constraints. The objective is to minimize the off-chip communication/wiring cost while improving the yield of an MCM or ASEM (using smaller partitions without violating I/O and area constraints). We formulate this as a 0/spl minus/1 quadratic programming problem with linear constraints. This paper describes the quantitative model and results from detailed partitioning of large benchmark VLSI circuits.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Yield-based system partitioning strategies for MCM and ASEM design\",\"authors\":\"S. Khan, V. Madisetti\",\"doi\":\"10.1109/MCMC.1994.292512\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a new quantitative approach to MCM and ASEM system partitioning under yield, I/O, and area constraints. The objective is to minimize the off-chip communication/wiring cost while improving the yield of an MCM or ASEM (using smaller partitions without violating I/O and area constraints). We formulate this as a 0/spl minus/1 quadratic programming problem with linear constraints. This paper describes the quantitative model and results from detailed partitioning of large benchmark VLSI circuits.<<ETX>>\",\"PeriodicalId\":292463,\"journal\":{\"name\":\"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-03-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MCMC.1994.292512\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCMC.1994.292512","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Yield-based system partitioning strategies for MCM and ASEM design
We propose a new quantitative approach to MCM and ASEM system partitioning under yield, I/O, and area constraints. The objective is to minimize the off-chip communication/wiring cost while improving the yield of an MCM or ASEM (using smaller partitions without violating I/O and area constraints). We formulate this as a 0/spl minus/1 quadratic programming problem with linear constraints. This paper describes the quantitative model and results from detailed partitioning of large benchmark VLSI circuits.<>