Izhikevich神经元模型的高效FPGA实现

2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI:10.1109/ISOCC50952.2020.9333014

Shiyu Yang, Peilin Liu, Jianwei Xue, Rongdi Sun, R. Ying

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引用次数: 2

摘要

本文提出了一种改进的Izhikevich神经元模型，用简单的基于二进制的移位运算代替复杂的乘法和除法运算。设计了一种基于计数器的加法器电路来解决多个神经元同时向一个神经元发射脉冲的问题。该模型在FPGA上实现。结果表明，该模型的硬件资源利用率比原模型降低了87.2%，最高工作频率从123.8MHz提高到291.8MHz。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An Efficient FPGA Implementation of Izhikevich Neuron Model

This paper presents a modified Izhikevich neuron model replacing complex multiplication and division operations with simple binary-based shift operations. A counter-based adder circuit is designed to address the problem that multiple neurons fire spikes simultaneously to one neuron. The proposed model is implemented on FPGA. Results show that the hardware resource utilization of the proposed model is reduced by 87.2% compared with that of the original model and the highest operating frequency is increased from 123.8MHz to 291.8MHz.

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2020 International SoC Design Conference (ISOCC)

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