模2k + 1加法器的逻辑

Jean P. Chinal
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引用次数: 1

摘要

考虑了任意k的模2k + 1加法器的设计,目标是实现尽可能规则的逻辑结构,以便于在大规模集成电路(LSI)中方便地实现。它显示了设计问题如何可以简化为递归生成减法信号,并在不同程度上将相应的逻辑与普通加法器的逻辑合并,或者,所谓的符号进位加法器的逻辑合并,该加法器一般是用递归和显式进位方案定义和设计的。给出了模2k + 1加法器的设计,其中一种是传统加法器,另一种是基于符号进位加法器,第三种是由符号进位方案导出的,其中减去信号的产生和进位逻辑是合并的。最后一种方案可以由两个向后递归链和五个或六个正向递归链组成。最后给出了该综合方案的两种基本变体,旨在尽可能减少单词中最显著位置所呈现的剩余逻辑结构不规则性
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The logic of modulo 2k + 1 adders
The design of modulo 2k + 1 adders for arbitrary k is considered, with the objective of achieving a logic structure as regular as possible so as to allow a convenient implementation in large-scale integration technology (LSI). It is shown how the design problem can be reduced to the recursive generation of a subtract signal and to the merging, in various degrees, of the corresponding logic with the logic of an ordinary adder or, alternately, of a so-called signed-carry adder which is defined and designed itself in general, with both recursive and explicit carry schemes. Modulo 2k + 1 adder designs are given, one with conventional adder, another based on signed-carry adder and a third, derived from the signed-carry scheme, where subtract signal generation and carry logic are merged. This last scheme can be set up with two backward recursion chains and five or six forward ones. Two more basic variants are finally indicated for this integrated scheme, aiming at reducing as much as possible the residual logic structure irregularity presented by the most significant position in the word
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