Design and Performance Analysis of 6T SRAM Cell on Different CMOS Technologies

Due to its special capacity to store data, static random-access memory (SRAM) has been a crucial memory technology in VLSI circuits and on System on Chip. SRAMs are frequently employed due to their enormous store capacity, quick access times, and low power requirements. Due to the fact that memories take up 60% to 70% of a chip, SRAM optimization has become a focus of research. We are attempting to design and implement a 6T SRAM in this project utilizing various CMOS technologies and the digital schematic and micro wind tool. As 6T SRAM is more practical to employ. Here, we evaluate SRAM’s performance in terms of Write delay, Read delay, Power Dissipation, and Average delay in order to determine which technology is the most advantageous.