纳米cmos电路的静态功耗:物理和建模

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI:10.1109/MIXDES.2007.4286142

W. Kuzmicz, E. Piwowarska, A. Pfitzner, D. Kasprowicz

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引用次数: 19

摘要

在栅极长度为90 nm及以下的CMOS数字ic中，由于泄漏电流过大而导致的静态功耗是一个主要问题。本文讨论了这些电流的物理和建模，特别强调了变异性及其对静态功耗和总功耗的统计分布的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Static Power Consumption in Nano-CMOS Circuits: Physics and Modelling

Static power consumption due to excessive leakage currents is a major problem in CMOS digital ICs with gate lengths of 90 nm and below. In this paper the physics and modelling of these currents is discussed, with special emphasis on variability and its effect on the statistical spread of the static power consumption and total power consumption.

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2007 14th International Conference on Mixed Design of Integrated Circuits and Systems

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