$\text{f}_{\text{T}}=305\ \text{GHz}，\ \text{f}_{\max}=537 \text{GHz}$ SiGe HBT在130nm和90nm CMOS上的集成

2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) Pub Date : 2018-10-01 DOI:10.1109/BCICTS.2018.8550922

D. Manger, W. Liebl, S. Boguth, B. Binder, K. Aufinger, C. Dahl, C. Hengst, A. Pribil, J. Oestreich, S. Rohmfeld, S. Rothenhaeusser, D. Tschumakow, J. Boeck

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引用次数: 0

摘要

本文报道了一个$\mathbf{f}_{\max}$为537GHz， $\mathbf{f}_{\text{T}}$为305GHz的SiGe-HBT制程模块在130nm BiCMOS技术上的成功实现。基于IHP之前所做的工作，HBT设备架构选择了一种改进的外延基链路工艺，因为它具有成熟的性能潜力。在电流模式逻辑(CML)中，环形振荡器门延迟的晶圆平均值为1.83ps，标准偏差为0.02ps。讨论了与90nm CMOS技术的集成选项，重点讨论了HBT和CMOS工艺模块在CMOS器件参数移位和潜在补救措施方面的相互作用。

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Integration of SiGe HBT with $\text{f}_{\text{T}}=305\ \text{GHz},\ \text{f}_{\max}=537 \text{GHz}$ in 130nm and 90nm CMOS

In this paper the successful implementation of a SiGe-HBT process module with an $\mathbf{f}_{\max}$ of 537GHz and an $\mathbf{f}_{\text{T}}$ of 305GHz in a 130nm BiCMOS technology is reported. A modified Epitaxial-Base-Link process, based on previous work done at IHP, was chosen for HBT device architecture, due to its proven performance potential. Ring oscillator gate-delays in current-mode-logic (CML) with a wafer mean value of 1.83ps and a standard deviation of 0.02ps were achieved. Integration options with a 90nm CMOS technology are discussed, with focus on the interaction of the HBT and CMOS process modules in terms of CMOS device parameter shift and potential remedies.

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2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)

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