Multiple-Core under Test Architecture for HOY Wireless Testing Platform

Test integration for heterogeneous cores under test has been a challenging problem in a system-on-chip (SoC) design. To integrate heterogeneous cores under test, the test wrapper should be capable of dealing with multiple-clock domain problems, at-speed testing problems, test power problems, etc. In this paper, we propose an alternative wrapper architecture that supports multiple clock domains, and therefore test operations can run (test) at system speed. Since each CUT has very different requirements, the test wrapper unavoidably needs to be re-designed for a new CUT. In order to reduce the manual effort, we propose to automatically generate test wrappers and the corresponding test programs based on the given configuration and test description for each CUT. We adopted the IEEE 1450.6 standard, a.k.a. Core Test Language (CTL), as the test description language in this work. Through the process, circuits can be tested with low overheads, and minimal intervention from designers will be required. We have successfully integrated a test wrapper generated by using our tool into a test chip which includes a Memory BIST and a Logic BIST and tapped out the chip in TSMC 0.18$\mu$m technology. The experiments showed that the area overhead of proposed architecture is only 0.02\% of chip area in the chip.