Small delay defect diagnosis through failure observation ordering

Rapidly increasing the yield for new process generations is crucial in achieving aggressive time-to-market requirements in semiconductor industry. As process scaling continues, subtle defects, primarily small delay defects that alter the timing of the circuits, are becoming increasingly common. An accurate diagnosis of small delay defects is essential in the identification of the cause of the defects and in the subsequent yield improvement. However, small and variable magnitude of small delay defects when coupled with the variable timing margins of the chips due to the process variation imposes inordinate challenges in small delay defect diagnosis. An approach for accurate small delay defect diagnosis that effectively prunes the candidate fault list based on the expected ordering of failure observation on outputs is proposed in this work.