D. Estryk, C. Verrastro, S. Marinsek, M. Belzunce, E. Venialgo
{"title":"正电子发射断层扫描仪的FPGA分层结构","authors":"D. Estryk, C. Verrastro, S. Marinsek, M. Belzunce, E. Venialgo","doi":"10.1109/SPL.2010.5483028","DOIUrl":null,"url":null,"abstract":"In this work, the AR-PET architecture is introduced and described. Its data acquisition system is composed of four layers of data processing with the purpose of computing the parameters as soon as possible to reduce data bandwidth for the next layer. FPGAs were used as main processing devices for the first three layers. The first layer computes pulse energy and timestamp, the second layer computes planar coordinates and the third layer does electronic collimation and spatial line of response computation. Some important issues, like time synchronization, data flow, trigger technique, configuration and programming buses are explained. The developed architecture was proved to be effective for PET scanner implementations.","PeriodicalId":372692,"journal":{"name":"2010 VI Southern Programmable Logic Conference (SPL)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"FPGA hierarchical architecture for a Positron Emission Tomography Scanner\",\"authors\":\"D. Estryk, C. Verrastro, S. Marinsek, M. Belzunce, E. Venialgo\",\"doi\":\"10.1109/SPL.2010.5483028\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, the AR-PET architecture is introduced and described. Its data acquisition system is composed of four layers of data processing with the purpose of computing the parameters as soon as possible to reduce data bandwidth for the next layer. FPGAs were used as main processing devices for the first three layers. The first layer computes pulse energy and timestamp, the second layer computes planar coordinates and the third layer does electronic collimation and spatial line of response computation. Some important issues, like time synchronization, data flow, trigger technique, configuration and programming buses are explained. The developed architecture was proved to be effective for PET scanner implementations.\",\"PeriodicalId\":372692,\"journal\":{\"name\":\"2010 VI Southern Programmable Logic Conference (SPL)\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-03-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 VI Southern Programmable Logic Conference (SPL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPL.2010.5483028\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 VI Southern Programmable Logic Conference (SPL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPL.2010.5483028","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA hierarchical architecture for a Positron Emission Tomography Scanner
In this work, the AR-PET architecture is introduced and described. Its data acquisition system is composed of four layers of data processing with the purpose of computing the parameters as soon as possible to reduce data bandwidth for the next layer. FPGAs were used as main processing devices for the first three layers. The first layer computes pulse energy and timestamp, the second layer computes planar coordinates and the third layer does electronic collimation and spatial line of response computation. Some important issues, like time synchronization, data flow, trigger technique, configuration and programming buses are explained. The developed architecture was proved to be effective for PET scanner implementations.