{"title":"在45纳米SOI CMOS中,100/202 GHz峰值功率为10.2/5.2 dBm的倍频器","authors":"Gang Liu, J. Jayamon, J. Buckwalter, P. Asbeck","doi":"10.1109/RFIC.2015.7337757","DOIUrl":null,"url":null,"abstract":"This paper presents frequency doublers with high output power for millimeter-wave applications. The circuits are fabricated using a 45nm SOI CMOS technology. A new circuit topology, combining a push-push doubler core with a cascaded stacked amplifier, has been implemented to increase the output power. The first doubler delivers 10.2 dBm peak power at 100 GHz output, with a 3-dB bandwidth from 88 to 104 GHz and DC-RF efficiency of 4.1%, while the second doubler has 5.2 dBm peak power at 202 GHz, with a 3-dB bandwidth from 180 to 212 GHz and DC-RF efficiency of 3.3%. To the authors' knowledge, these are the highest powers reported for silicon frequency doublers in similar frequency ranges to date. The 200 GHz doubler also provides the highest on-chip power from a single-element signal generation circuit without power combining.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"32","resultStr":"{\"title\":\"Frequency doublers with 10.2/5.2 dBm peak power at 100/202 GHz in 45nm SOI CMOS\",\"authors\":\"Gang Liu, J. Jayamon, J. Buckwalter, P. Asbeck\",\"doi\":\"10.1109/RFIC.2015.7337757\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents frequency doublers with high output power for millimeter-wave applications. The circuits are fabricated using a 45nm SOI CMOS technology. A new circuit topology, combining a push-push doubler core with a cascaded stacked amplifier, has been implemented to increase the output power. The first doubler delivers 10.2 dBm peak power at 100 GHz output, with a 3-dB bandwidth from 88 to 104 GHz and DC-RF efficiency of 4.1%, while the second doubler has 5.2 dBm peak power at 202 GHz, with a 3-dB bandwidth from 180 to 212 GHz and DC-RF efficiency of 3.3%. To the authors' knowledge, these are the highest powers reported for silicon frequency doublers in similar frequency ranges to date. The 200 GHz doubler also provides the highest on-chip power from a single-element signal generation circuit without power combining.\",\"PeriodicalId\":121490,\"journal\":{\"name\":\"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-05-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"32\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2015.7337757\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2015.7337757","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Frequency doublers with 10.2/5.2 dBm peak power at 100/202 GHz in 45nm SOI CMOS
This paper presents frequency doublers with high output power for millimeter-wave applications. The circuits are fabricated using a 45nm SOI CMOS technology. A new circuit topology, combining a push-push doubler core with a cascaded stacked amplifier, has been implemented to increase the output power. The first doubler delivers 10.2 dBm peak power at 100 GHz output, with a 3-dB bandwidth from 88 to 104 GHz and DC-RF efficiency of 4.1%, while the second doubler has 5.2 dBm peak power at 202 GHz, with a 3-dB bandwidth from 180 to 212 GHz and DC-RF efficiency of 3.3%. To the authors' knowledge, these are the highest powers reported for silicon frequency doublers in similar frequency ranges to date. The 200 GHz doubler also provides the highest on-chip power from a single-element signal generation circuit without power combining.