无结硅纳米线晶体管的原子尺度模拟

Ulis 2011 Ultimate Integration on Silicon Pub Date : 1900-01-01 DOI:10.1109/ulis.2011.5757976

L. Ansari, B. Feldman, G. Fagas, J. Colinge, J. Greer

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引用次数: 2

摘要

我们在密度泛函理论(DFT)框架内模拟了具有3nm栅极长度的硅纳米线无结晶体管。我们探索了晶体管对源漏偏置(VDS)和栅极电压(Vg)的响应。同时，对线材截面上体积和表面吸附原子的影响进行了评价。

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Atomic scale simulation of a junctionless silicon nanowire transistor

We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.

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Ulis 2011 Ultimate Integration on Silicon

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