{"title":"高温溅射原位硅化亚四分之一微米水化钛技术","authors":"K. Fujii, K. Kikuta, T. Kikkawa","doi":"10.1109/VLSIT.1995.520856","DOIUrl":null,"url":null,"abstract":"A new titanium (Ti) salicide technology with in-situ silicidation using high-temperature sputtering has been developed. This process enhances TiSi/sub 2/ phase transition from C49 to C54 without agglomeration, which results in achieving silicidation in 0.2 /spl mu/m gates and 0.4 /spl mu/m diffusion layers. A sheet resistance less than 6/spl Omega///spl square/ can be obtained for both n/sup +/ and p/sup +/ silicide gates. CMOS transistors having 0.09 /spl mu/m effective channel length were successfully formed using the in-situ silicidation technique.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"Sub-quarter micron titanium salicide technology with in-situ silicidation using high-temperature sputtering\",\"authors\":\"K. Fujii, K. Kikuta, T. Kikkawa\",\"doi\":\"10.1109/VLSIT.1995.520856\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new titanium (Ti) salicide technology with in-situ silicidation using high-temperature sputtering has been developed. This process enhances TiSi/sub 2/ phase transition from C49 to C54 without agglomeration, which results in achieving silicidation in 0.2 /spl mu/m gates and 0.4 /spl mu/m diffusion layers. A sheet resistance less than 6/spl Omega///spl square/ can be obtained for both n/sup +/ and p/sup +/ silicide gates. CMOS transistors having 0.09 /spl mu/m effective channel length were successfully formed using the in-situ silicidation technique.\",\"PeriodicalId\":328379,\"journal\":{\"name\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"volume\":\"74 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1995.520856\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 Symposium on VLSI Technology. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1995.520856","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Sub-quarter micron titanium salicide technology with in-situ silicidation using high-temperature sputtering
A new titanium (Ti) salicide technology with in-situ silicidation using high-temperature sputtering has been developed. This process enhances TiSi/sub 2/ phase transition from C49 to C54 without agglomeration, which results in achieving silicidation in 0.2 /spl mu/m gates and 0.4 /spl mu/m diffusion layers. A sheet resistance less than 6/spl Omega///spl square/ can be obtained for both n/sup +/ and p/sup +/ silicide gates. CMOS transistors having 0.09 /spl mu/m effective channel length were successfully formed using the in-situ silicidation technique.
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