{"title":"FFT处理器并发故障检测方案","authors":"M. Tsunoyama, M. Uenoyama, T. Kabasawa","doi":"10.1109/ATS.1997.643928","DOIUrl":null,"url":null,"abstract":"This paper proposes a concurrent fault-detection scheme for FFT processors. In the scheme, fault detection is made by comparing the pair of outputs from butterfly units based on the FFT algorithm. The hardware overhead for the scheme is O(N) where N is the number of input data. This scheme requires no extra computations for locating a pair of faulty butterfly units, therefore, the scheme can be used for highly reliable real-time systems.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A concurrent fault-detection scheme for FFT processors\",\"authors\":\"M. Tsunoyama, M. Uenoyama, T. Kabasawa\",\"doi\":\"10.1109/ATS.1997.643928\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a concurrent fault-detection scheme for FFT processors. In the scheme, fault detection is made by comparing the pair of outputs from butterfly units based on the FFT algorithm. The hardware overhead for the scheme is O(N) where N is the number of input data. This scheme requires no extra computations for locating a pair of faulty butterfly units, therefore, the scheme can be used for highly reliable real-time systems.\",\"PeriodicalId\":330767,\"journal\":{\"name\":\"Proceedings Sixth Asian Test Symposium (ATS'97)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-11-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Sixth Asian Test Symposium (ATS'97)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.1997.643928\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Sixth Asian Test Symposium (ATS'97)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1997.643928","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A concurrent fault-detection scheme for FFT processors
This paper proposes a concurrent fault-detection scheme for FFT processors. In the scheme, fault detection is made by comparing the pair of outputs from butterfly units based on the FFT algorithm. The hardware overhead for the scheme is O(N) where N is the number of input data. This scheme requires no extra computations for locating a pair of faulty butterfly units, therefore, the scheme can be used for highly reliable real-time systems.