M. Ershov, F. Nemati, R. Gupta, V. Gopalakrishnan, R. Gooty, M. Tarabbia, K. Yang, S. Banna, D. Hayes, H. Cho, S. Robins
{"title":"SOI T-RAM存储技术中用于后门控制的衬底掺杂优化","authors":"M. Ershov, F. Nemati, R. Gupta, V. Gopalakrishnan, R. Gooty, M. Tarabbia, K. Yang, S. Banna, D. Hayes, H. Cho, S. Robins","doi":"10.1109/SOI.2005.1563593","DOIUrl":null,"url":null,"abstract":"This paper presents various considerations for substrate doping optimization in SOI T-RAM technology. Back gate (substrate voltage) control is used in an SOI T-RAM technology for optimizing cell characteristics. However, it is reported for the first time that typical low-doped substrates used in SOI logic technologies can create unusually slow transient effects in T-RAM cell. It is also demonstrated that the optimization of substrate doping resolves this slow transient problem and improves back gate control of SOI T-RAM memory arrays.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Optimization of substrate doping for back-gate control in SOI T-RAM memory technology\",\"authors\":\"M. Ershov, F. Nemati, R. Gupta, V. Gopalakrishnan, R. Gooty, M. Tarabbia, K. Yang, S. Banna, D. Hayes, H. Cho, S. Robins\",\"doi\":\"10.1109/SOI.2005.1563593\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents various considerations for substrate doping optimization in SOI T-RAM technology. Back gate (substrate voltage) control is used in an SOI T-RAM technology for optimizing cell characteristics. However, it is reported for the first time that typical low-doped substrates used in SOI logic technologies can create unusually slow transient effects in T-RAM cell. It is also demonstrated that the optimization of substrate doping resolves this slow transient problem and improves back gate control of SOI T-RAM memory arrays.\",\"PeriodicalId\":116606,\"journal\":{\"name\":\"2005 IEEE International SOI Conference Proceedings\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE International SOI Conference Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOI.2005.1563593\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International SOI Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.2005.1563593","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimization of substrate doping for back-gate control in SOI T-RAM memory technology
This paper presents various considerations for substrate doping optimization in SOI T-RAM technology. Back gate (substrate voltage) control is used in an SOI T-RAM technology for optimizing cell characteristics. However, it is reported for the first time that typical low-doped substrates used in SOI logic technologies can create unusually slow transient effects in T-RAM cell. It is also demonstrated that the optimization of substrate doping resolves this slow transient problem and improves back gate control of SOI T-RAM memory arrays.
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