Robert Bai, S. Kulkarni, Wesley Kwong, A. Srivastava, D. Sylvester, D. Blaauw
{"title":"采用双电源和双阈值电压的32位ARM处理器的实现","authors":"Robert Bai, S. Kulkarni, Wesley Kwong, A. Srivastava, D. Sylvester, D. Blaauw","doi":"10.1109/ISVLSI.2003.1183366","DOIUrl":null,"url":null,"abstract":"With the explosion of portable electronic devices, power efficient processors have become increasingly important. In this paper we present a set of circuit techniques to implement a 32-bit low-power ARM processor, found commonly in embedded systems, using a six metal layer 0.18 /spl mu/m TSMC process. Our methodology is based on Clustered Voltage Scaling (CVS) and dual-V/sub th/ techniques aiming to reduce both dynamic power and static power simultaneously.","PeriodicalId":299309,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","volume":"148 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"An implementation of a 32-bit ARM processor using dual power supplies and dual threshold voltages\",\"authors\":\"Robert Bai, S. Kulkarni, Wesley Kwong, A. Srivastava, D. Sylvester, D. Blaauw\",\"doi\":\"10.1109/ISVLSI.2003.1183366\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With the explosion of portable electronic devices, power efficient processors have become increasingly important. In this paper we present a set of circuit techniques to implement a 32-bit low-power ARM processor, found commonly in embedded systems, using a six metal layer 0.18 /spl mu/m TSMC process. Our methodology is based on Clustered Voltage Scaling (CVS) and dual-V/sub th/ techniques aiming to reduce both dynamic power and static power simultaneously.\",\"PeriodicalId\":299309,\"journal\":{\"name\":\"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.\",\"volume\":\"148 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-02-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2003.1183366\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2003.1183366","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An implementation of a 32-bit ARM processor using dual power supplies and dual threshold voltages
With the explosion of portable electronic devices, power efficient processors have become increasingly important. In this paper we present a set of circuit techniques to implement a 32-bit low-power ARM processor, found commonly in embedded systems, using a six metal layer 0.18 /spl mu/m TSMC process. Our methodology is based on Clustered Voltage Scaling (CVS) and dual-V/sub th/ techniques aiming to reduce both dynamic power and static power simultaneously.