A two-step layout-in-the-loop design automation tool

There exists circuit sizing and layout generation tools for analog circuit designers to speed up the design process. Generally, these tools handle the circuit sizing and the layout generation processes separately, which may cause performance failures and laborious redesign iterations. Recently, new tools have been developed which simultaneously take care of circuit sizing and layout generation. However, they either suffer from long run times or limited accuracy of the utilized parasitic model. This paper presents a complete layout-aware design automation tool for analog circuits. The proposed tool combines a simulation-based circuit sizing tool with a template-based layout generation tool. The layout-induced parasitics are automatically extracted via a commercially available extractor. To reduce the run time cost originating from parasitic extraction, a two step methodology is followed, where infeasible solutions are prohibited from costly extraction process.