Smart behavioral netlist simulation for SEU protection verification

This paper presents a novel approach to verify the correct implementation of Triple Modular Redundancy (TMR) for the memory elements of a given netlist using formal analysis. The purpose is detecting any issues that might incur during the use of automatic tools for TMR insertion, optimization, place and route, etc. Our analysis does not require a testbench and can perform full, exhaustive coverage within less than an hour even for large designs. This is achieved by applying a divide et impera approach, splitting the circuit into smaller submodules without loss of generality, instead of applying formal verification to the whole netlist at once. The methodology has been applied to a production netlist of the LEON2-FT processor that reported errors during radiation testing, successfully showing its TMR implementation issues.