晶体管级单片3D标准单元布局优化,实现全芯片静态电源完整性

B. W. Ku, Taigon Song, A. Nieuwoudt, S. Lim
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引用次数: 7

摘要

现有的晶体管级单片3D (T-M3D)标准单元布局基于折叠方案,其中下拉网络简单地折叠并放置在上拉网络的顶部。在本文中,我们提出了一种新的布局方法,即拼接方案,旨在提高电池的性能和功率完整性。我们对每种布局方案进行了广泛的分析,并评估了拼接方案的时序/功率优势。由于T-M3D布局中的地面和电源轨与折叠方案重叠,我们还提出了折叠T-M3D ic供电网络的设计方法,以评估T-M3D单元布局方案对静态功率完整性的影响。与同等性能的2D ic相比,拼接T-M3D ic最多可节省6%的功耗,节省44%的面积,在14nm技术节点上仅增加1%的静态ir下降,而折叠T-M3D ic则会严重降低静态功耗完整性,从而导致可靠性问题。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity
Existing transistor-level monolithic 3D (T-M3D) standard cell layouts are based on the folding scheme, in which the pull-down network is simply folded and placed on top of the pull-up network. In this paper, we propose a new layout method, the stitching scheme, targeted towards improved cell performance and power integrity. We perform extensive analysis on each layout scheme and evaluate the timing/power benefits of the stitching scheme. Since the ground and power rails overlap in the T-M3D layouts with the folding scheme, we also present a design methodology for the power delivery network of folding T-M3D ICs to evaluate the impact of the T-M3D cell layout scheme on static power integrity. Compared to 2D ICs at iso-performance, stitching T-M3D ICs show a maximum of 6% power savings, 44% area savings with only 1% more static IR-drop in the 14nm technology node while folding T-M3D ICs undergo serious degradation in static power integrity, causing a reliability issue.
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