{"title":"使用标准VLSI路由工具的嵌入式fpga互连路由","authors":"Thomas Coenen, J. Schleifer, O. Weiss, T. Noll","doi":"10.1109/ISSOC.2010.5625549","DOIUrl":null,"url":null,"abstract":"Embedded Field Programmable Gate Arrays (eFPGAs) offer an attractive way to integrate configurable hardware accelerators for signal processing tasks into systems on chips. To achieve maximum efficiency it is furthermore advisable to adapt a parametrizable eFPGA architecture to a specific class of applications. Conventional mapping tools however accommodate only a single architecture resulting in the need of a portable mapping tool. In this paper we propose a method to employ standard VLSI routing tools to solve the eFPGA routing problem for parametrizable architectures.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"09 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Interconnect routing of embedded FPGAs using standard VLSI routing tools\",\"authors\":\"Thomas Coenen, J. Schleifer, O. Weiss, T. Noll\",\"doi\":\"10.1109/ISSOC.2010.5625549\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Embedded Field Programmable Gate Arrays (eFPGAs) offer an attractive way to integrate configurable hardware accelerators for signal processing tasks into systems on chips. To achieve maximum efficiency it is furthermore advisable to adapt a parametrizable eFPGA architecture to a specific class of applications. Conventional mapping tools however accommodate only a single architecture resulting in the need of a portable mapping tool. In this paper we propose a method to employ standard VLSI routing tools to solve the eFPGA routing problem for parametrizable architectures.\",\"PeriodicalId\":252669,\"journal\":{\"name\":\"2010 International Symposium on System on Chip\",\"volume\":\"09 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Symposium on System on Chip\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSOC.2010.5625549\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Symposium on System on Chip","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSOC.2010.5625549","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Interconnect routing of embedded FPGAs using standard VLSI routing tools
Embedded Field Programmable Gate Arrays (eFPGAs) offer an attractive way to integrate configurable hardware accelerators for signal processing tasks into systems on chips. To achieve maximum efficiency it is furthermore advisable to adapt a parametrizable eFPGA architecture to a specific class of applications. Conventional mapping tools however accommodate only a single architecture resulting in the need of a portable mapping tool. In this paper we propose a method to employ standard VLSI routing tools to solve the eFPGA routing problem for parametrizable architectures.