不平衡缓存系统

D. Rhodes, W. Wolf
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引用次数: 1

摘要

介绍并分析了非平衡分层缓存系统的新概念。这种方法通过允许不同的内存引用(例如,在一个地址空间内可能不均匀地划分)服从于不同级别的缓存以及每个级别的不同数量的缓存来推广现有的缓存结构。假设在特定级别上的总缓存大小是固定的,很容易证明至少存在一个分割的缓存结构,其缺失率与单个统一缓存相同。然而,通过使用替代实现,该方法可以显著降低失误率,如模拟所示。具体来说,SPEC95基准测试用于证明该技术对一般使用是有效的,但它可能对嵌入式系统更有用,其中内存访问模式可以更完全地控制(即通过编译器)。除了提高失误率之外,另一个优点是多个较小缓存的命中时间可能比单个较大缓存的命中时间要短。缺点,但容易克服,电气方面也进行了讨论。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Unbalanced cache systems
The new concept of an unbalanced, hierarchically-divided cache memory system is introduced and analyzed. This approach generalizes existing cache structures by allowing different memory references (e.g. as possibly unevenly divided within an address-space) to be subject to various levels of caching as well as varied amounts of cache at each level. Under the assumption that the total cache size at a particular level is fixed, it is easily shown that at least one divided cache structure exists for which the miss-rate is the same as a single unified cache. By using alternate implementations, however, the method may provide a significant decrease in miss-rates as is shown via simulations. Specifically, SPEC95 benchmarks are used to demonstrate that the technique is effective for general usage but it may be even more useful for embedded systems where memory access patterns can be more fully controlled (i.e. via the compiler). In addition to improved miss-rates, another advantage is that the hit-time for multiple smaller caches may be smaller than for a single larger cache. Disadvantageous, but readily surmountable, electrical aspects are also discussed.
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