A generalized hybrid multilevel inverter with reduced number of switches

This paper demonstrates about a novel multilevel inverter (MLI) structure designed with reduced number of switches that can be worked in both symmetric as well as asymmetric DC link voltages. Also, the proposed model can be extended to a generalized n level inverter. The carrier based, Level shifted PWM (LS-PWM) technique is used to generate the gate pulses of the proposed inverter. The proposed MLI is simulated using the MATLAB/SIMULINK platform and verified by the experimental results. The simulation results of a specimen seven level symmetrical inverter as well for a nine-level asymmetrical inverter is presented in the paper. The corresponding experimental results are also presented for the different modulation index.