{"title":"一种基于机器描述表的指令调度器,用于提高QHRC RISC系统的流水线执行并行性","authors":"L. Sanli, Fu Xinggang","doi":"10.1109/TENCON.1993.319917","DOIUrl":null,"url":null,"abstract":"This paper presents a parameterized instruction scheduling algorithm based on machine description table for QHRC RISC system, having a 3-5 stage pipeline structure. It would provide considerable flexibility for instruction scheduling, improving execution efficiency for rapidly upgrading RISC machines. And, using this instruction scheduler as a tool, the effect of several methods for solving instruction interlock problem has been analysed. Finally, a high performance approach combining the hardware feasibility and software effectiveness for solving instruction interlock problem and enhancing pipeline execution parallelism is given.<<ETX>>","PeriodicalId":110496,"journal":{"name":"Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A machine-description table based instruction scheduler for improving pipeline execution parallelism on QHRC RISC system\",\"authors\":\"L. Sanli, Fu Xinggang\",\"doi\":\"10.1109/TENCON.1993.319917\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a parameterized instruction scheduling algorithm based on machine description table for QHRC RISC system, having a 3-5 stage pipeline structure. It would provide considerable flexibility for instruction scheduling, improving execution efficiency for rapidly upgrading RISC machines. And, using this instruction scheduler as a tool, the effect of several methods for solving instruction interlock problem has been analysed. Finally, a high performance approach combining the hardware feasibility and software effectiveness for solving instruction interlock problem and enhancing pipeline execution parallelism is given.<<ETX>>\",\"PeriodicalId\":110496,\"journal\":{\"name\":\"Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-10-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TENCON.1993.319917\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TENCON.1993.319917","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A machine-description table based instruction scheduler for improving pipeline execution parallelism on QHRC RISC system
This paper presents a parameterized instruction scheduling algorithm based on machine description table for QHRC RISC system, having a 3-5 stage pipeline structure. It would provide considerable flexibility for instruction scheduling, improving execution efficiency for rapidly upgrading RISC machines. And, using this instruction scheduler as a tool, the effect of several methods for solving instruction interlock problem has been analysed. Finally, a high performance approach combining the hardware feasibility and software effectiveness for solving instruction interlock problem and enhancing pipeline execution parallelism is given.<>