一个7位500mhz闪存ADC

2014 First International Conference on Computational Systems and Communications (ICCSC) Pub Date : 2014-12-01 DOI:10.1109/COMPSC.2014.7032624

A. Jayakumar, K. Vishnu

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引用次数: 7

摘要

本文介绍了一种高速、高分辨率CMOS Flash模数转换器的系统设计。采用gpdk90纳米CMOS技术，采用1.2 v模拟电源电压，在cadence环境下实现了一个7位闪存ADC。该转换器的信噪比为39.3574dB，无杂散动态范围为40.7547dB，采样率为500MHz。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 7-bit 500-MHz flash ADC

This paper describes the systematic design of a high speed and high resolution CMOS Flash Analog-To-Digital Converter. A 7-bit flash ADC is implemented in cadence environment using gpdk90-nm CMOS technology with a 1.2-V analog supply voltage. The converter achieves a signal-to-(noise + distortion) ratio of 39.3574dB and signal-to-spurious-free-dynamic-range of 40.7547dB with a sampling rate of 500MHz.

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2014 First International Conference on Computational Systems and Communications (ICCSC)

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