An implemented VLSI architecture of inverse quantizer for AVS HDTV video decoder

AVS is Chinese new audio and video coding standard. A pipeline-based architecture of inverse quantizer for AVS video standard is proposed in this paper. Due to using one-pass processing for run length decoding, inverse scan and inverse quantization, the architecture can save many buffers, which are used to store intermediate results during multi-pass processing. Furthermore, the processing speed is up to one coefficient per clock cycle. This architecture has been described in Verilog HDL, simulated with VCS digital simulator, and synthesized using 0.18mum CMOS cells library by Synopsys design compiler. The circuit totally costs about 13.7k logic gates when running at 200MHz. Simulation results show that the architecture can support real-time inverse quantization for HDTV (1280times720, 60fps) video. This architecture has been implemented in a single chip HDTV decoder for AVS video and audio