终极平面和纳米线mosfet的通道材料优化:理论探索

Jing Wang, M. Lundstrom
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引用次数: 5

摘要

现代mosfet的通道长度低于50纳米,十亿晶体管逻辑芯片已经问世。摩尔定律仍在继续,但MOSFET缩放的终结近在眼前。许多研究人员正在探索新的材料和器件结构,以推动MOS技术走向基本极限。用应变硅,SiGe,甚至III-V通道的mosfet都是可能的,由纳米线或纳米管制成的一维通道也是可能的。在本文中,我们从理论上研究了通道材料特性(即E(k))和器件结构(即2D平面与ID纳米线)对弹道mosfet最终性能的影响。目的是为最终的平面/纳米线mosfet确定最佳沟道材料。结果表明,当输运有效质量较小时,器件性能下降,且平面mosfet和纳米线mosfet表现不同。不同的通道材料在带边处表现出不同的E(k)关系和有效质量。为了实现高器件性能,人们可能会期望光输运有效质量是最好的,因为它提供了高载流子注入速度。另一方面,光的有效质量也会导致较低的量子(或半导体)电容,从而降低器件的导通电流。当通道长度足够小时,在较小的输运有效质量下会发生强烈的源漏隧穿。隧道效应降低了场效应管的亚阈值特性,从而降低了相同off电流的on电流。由于这些原因,对于给定的器件结构,可能存在最佳输运有效质量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Channel material optimization for the ultimate planar and nanowire mosfets: a theoretical exploration
Modem MOSFETs have channel lengths below 50 nm, and billion transistor logic chips have arrived. Moore's Law continues, but the end of MOSFET scaling is in sight. Many researchers are exploring new materials and device structures to push MOS technology towards fundamental limits. MOSFETs with strained silicon, SiGe, or even III-V channels are possibilities, as are one-dimensional channels made from nanowires or nanotubes. In this paper, we theoretically examine the impact of the channel material property (i.e., E(k)) and device structure (i.e., 2D planar vs. ID nanowire) on the ultimate performance of ballistic MOSFETs. The objective is to identify an optimum channel material for the ultimate planar/nanowire MOSFETs. The results show that when the transport effective mass is small, it degrades device performance, and that planar and nanowire MOSFETs behave differently. Different channel materials display different E(k) relations and different effective mass at the band-edge. To achieve high device performance, one might expect that a light transport effective mass would be best since it offers a high carrier injection velocity. On the other hand, a light effective mass also leads to a lower quantum (or semiconductor) capacitance, which degrades the ON-current of the device. When the channel length is sufficiently small, strong source-to-drain (S/D) tunneling occurs at a small transport effective mass. Tunneling degrades the subthreshold characteristics of the FET and consequently lowers the ON-current for the same OFF-current. For these reasons, an optimum transport effective mass may exist for a given device structure.
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