T. Das, C. Mahata, G. Dalapati, D. Chi, G. Sutradhar, P. K. Bose, C. Maiti
{"title":"Si钝化p-GaAs上ZrO2栅极介电介质的可靠性和电荷捕获特性","authors":"T. Das, C. Mahata, G. Dalapati, D. Chi, G. Sutradhar, P. K. Bose, C. Maiti","doi":"10.1109/IPFA.2009.5232683","DOIUrl":null,"url":null,"abstract":"Reliability characteristics of ZrO2 gate dielectric films on p-GaAs with ultrathin Silicon (Si) interfacial passivated layer have been investigated. Results of a systematic study on the impacts of post deposition annealing (PDA) on the physical and electrical properties of RF-sputtered ZrO2 dielectric layers on Si-passivated p-GaAs substrates are reported. The electrical characteristics have been performed using C-V, I-V, CVS and CCS to understand the reliability and the interface trapping behaviour of TaN/ZrO2/Si/p-GaAs gate stack. Low positive charge trapping after N2 annealing was observed for different constant voltage and current stressing conditions.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Reliability and charge trapping properties of ZrO2 gate dielectric on Si passivated p-GaAs\",\"authors\":\"T. Das, C. Mahata, G. Dalapati, D. Chi, G. Sutradhar, P. K. Bose, C. Maiti\",\"doi\":\"10.1109/IPFA.2009.5232683\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Reliability characteristics of ZrO2 gate dielectric films on p-GaAs with ultrathin Silicon (Si) interfacial passivated layer have been investigated. Results of a systematic study on the impacts of post deposition annealing (PDA) on the physical and electrical properties of RF-sputtered ZrO2 dielectric layers on Si-passivated p-GaAs substrates are reported. The electrical characteristics have been performed using C-V, I-V, CVS and CCS to understand the reliability and the interface trapping behaviour of TaN/ZrO2/Si/p-GaAs gate stack. Low positive charge trapping after N2 annealing was observed for different constant voltage and current stressing conditions.\",\"PeriodicalId\":210619,\"journal\":{\"name\":\"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-07-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.2009.5232683\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2009.5232683","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reliability and charge trapping properties of ZrO2 gate dielectric on Si passivated p-GaAs
Reliability characteristics of ZrO2 gate dielectric films on p-GaAs with ultrathin Silicon (Si) interfacial passivated layer have been investigated. Results of a systematic study on the impacts of post deposition annealing (PDA) on the physical and electrical properties of RF-sputtered ZrO2 dielectric layers on Si-passivated p-GaAs substrates are reported. The electrical characteristics have been performed using C-V, I-V, CVS and CCS to understand the reliability and the interface trapping behaviour of TaN/ZrO2/Si/p-GaAs gate stack. Low positive charge trapping after N2 annealing was observed for different constant voltage and current stressing conditions.