收缩压阵列实现基于块的Hopfield神经网络模式关联

IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings. Pub Date : 2003-02-20 DOI:10.1109/ISVLSI.2003.1183471

Ming-Jung Seow, H. T. Ngo, V. Asari

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引用次数: 1

摘要

本文提出了一种采用全数字电路的基于块的Hopfield神经网络结构的收缩阵列实现方法。该设计基于将Hopfield神经网络的能量方程重写为收缩(或模块化)形式。通过应用各种二进制输入来评估所提出的体系结构的性能，并观察到网络提供了大量的并行性，并且可以通过级联相同的芯片进行扩展。

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Systolic array implementation of block based Hopfield neural network for pattern association

This paper suggests a systolic array implementation of block based Hopfield neural network architecture using completely digital circuits. The design is based on rewriting the energy equation of the Hopfield neural network to a systolic (or modular) form. The performance of the proposed architecture is evaluated by applying various binary inputs and it is observed that the network provides massive parallelism and can be extended by cascading identical chips.

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IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.

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