{"title":"基于数字信号处理器(DSP)的Reed-Solomon解码器设计","authors":"T. Todoroki, S. Miura","doi":"10.1109/ITS.1990.175644","DOIUrl":null,"url":null,"abstract":"The design of a Reed-Solomon (RS) decoder using two digital signal processors (DSP) is discussed. The RS code is a (255, 223) block code of 8-bit symbols which is capable of correcting up to 16 symbol errors. Any primitive polynomial of GF(2/sup 8/) and generator polynomial for a systematic code can be used. The algorithm used for computing the error-locator polynomial is an Euclid's algorithm. For high-speed decoding, finite field multiplication is carried out by using log and antilog tables in the DSP. A 275 kb/s maximum data transmission rate and 4000 bits for the decoding delay were obtained by using this decoder.<<ETX>>","PeriodicalId":405932,"journal":{"name":"SBT/IEEE International Symposium on Telecommunications","volume":"83 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of a Reed-Solomon decoder using a digital signal processor (DSP)\",\"authors\":\"T. Todoroki, S. Miura\",\"doi\":\"10.1109/ITS.1990.175644\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design of a Reed-Solomon (RS) decoder using two digital signal processors (DSP) is discussed. The RS code is a (255, 223) block code of 8-bit symbols which is capable of correcting up to 16 symbol errors. Any primitive polynomial of GF(2/sup 8/) and generator polynomial for a systematic code can be used. The algorithm used for computing the error-locator polynomial is an Euclid's algorithm. For high-speed decoding, finite field multiplication is carried out by using log and antilog tables in the DSP. A 275 kb/s maximum data transmission rate and 4000 bits for the decoding delay were obtained by using this decoder.<<ETX>>\",\"PeriodicalId\":405932,\"journal\":{\"name\":\"SBT/IEEE International Symposium on Telecommunications\",\"volume\":\"83 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"SBT/IEEE International Symposium on Telecommunications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ITS.1990.175644\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"SBT/IEEE International Symposium on Telecommunications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ITS.1990.175644","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a Reed-Solomon decoder using a digital signal processor (DSP)
The design of a Reed-Solomon (RS) decoder using two digital signal processors (DSP) is discussed. The RS code is a (255, 223) block code of 8-bit symbols which is capable of correcting up to 16 symbol errors. Any primitive polynomial of GF(2/sup 8/) and generator polynomial for a systematic code can be used. The algorithm used for computing the error-locator polynomial is an Euclid's algorithm. For high-speed decoding, finite field multiplication is carried out by using log and antilog tables in the DSP. A 275 kb/s maximum data transmission rate and 4000 bits for the decoding delay were obtained by using this decoder.<>
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