低功耗CMOS管道突发SRAM的设计

ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425) Pub Date : 2000-11-13 DOI:10.1109/SMELEC.2000.932471

C.L. Lee, R. Wagiran, B.S. Suparjo, R. Sidek

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摘要

提出了一种低功耗管道突发同步静态随机存取存储器。本文回顾了利用分字线结构降低电容的低功耗技术，以及利用电流模式感应技术降低检测放大器的工作电压的技术。SRAM具有地址突发模式操作和选择性字节写入操作。

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The design of low-power CMOS pipelined-burst SRAM

This paper presents a low power pipelined-burst synchronized static random access memory. Low-power techniques are reviewed for capacitance reduction by using a divided word-line structure, and for operating voltage reduction by using a current-mode sensing technique for the sense amplifier. The SRAM is designed with address burst mode operation and selective byte write operation.

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ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)

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