{"title":"用多路复用器合成逻辑函数的遗传规划方法","authors":"A. H. Aguirre, B. Buckles, C. C. Coello","doi":"10.1109/EH.1999.785434","DOIUrl":null,"url":null,"abstract":"This paper presents an approach based on the use of genetic programming to synthesize logic functions. The proposed approach uses the 1-control line multiplexer as the only design unit, defining any logic function (defined by a truth table) through the replication of this single unit. Our fitness function first explores the search space trying to find a feasible design and then concentrates on the minimization of such (fully feasible) circuit. The proposed approach is illustrated using several sample Boolean functions.","PeriodicalId":234639,"journal":{"name":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"37","resultStr":"{\"title\":\"A genetic programming approach to logic function synthesis by means of multiplexers\",\"authors\":\"A. H. Aguirre, B. Buckles, C. C. Coello\",\"doi\":\"10.1109/EH.1999.785434\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an approach based on the use of genetic programming to synthesize logic functions. The proposed approach uses the 1-control line multiplexer as the only design unit, defining any logic function (defined by a truth table) through the replication of this single unit. Our fitness function first explores the search space trying to find a feasible design and then concentrates on the minimization of such (fully feasible) circuit. The proposed approach is illustrated using several sample Boolean functions.\",\"PeriodicalId\":234639,\"journal\":{\"name\":\"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-07-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"37\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EH.1999.785434\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the First NASA/DoD Workshop on Evolvable Hardware","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EH.1999.785434","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A genetic programming approach to logic function synthesis by means of multiplexers
This paper presents an approach based on the use of genetic programming to synthesize logic functions. The proposed approach uses the 1-control line multiplexer as the only design unit, defining any logic function (defined by a truth table) through the replication of this single unit. Our fitness function first explores the search space trying to find a feasible design and then concentrates on the minimization of such (fully feasible) circuit. The proposed approach is illustrated using several sample Boolean functions.