{"title":"服从设计","authors":"P. Marsh","doi":"10.1049/ESS:20060204","DOIUrl":null,"url":null,"abstract":"Only by pre-empting yield issues at an early stage can future designs come in under budget - an emerging breed of tools and modeling techniques may hold the answer. Yield-aware synthesis tools provide an opportunity to perform a more wholesale logic optimization and restructuring, maximizing yield concurrently with other design goals.","PeriodicalId":132835,"journal":{"name":"Electronic Systems and Software","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Yielding to design\",\"authors\":\"P. Marsh\",\"doi\":\"10.1049/ESS:20060204\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Only by pre-empting yield issues at an early stage can future designs come in under budget - an emerging breed of tools and modeling techniques may hold the answer. Yield-aware synthesis tools provide an opportunity to perform a more wholesale logic optimization and restructuring, maximizing yield concurrently with other design goals.\",\"PeriodicalId\":132835,\"journal\":{\"name\":\"Electronic Systems and Software\",\"volume\":\"62 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-10-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electronic Systems and Software\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1049/ESS:20060204\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electronic Systems and Software","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1049/ESS:20060204","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Only by pre-empting yield issues at an early stage can future designs come in under budget - an emerging breed of tools and modeling techniques may hold the answer. Yield-aware synthesis tools provide an opportunity to perform a more wholesale logic optimization and restructuring, maximizing yield concurrently with other design goals.
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