3D IC architecture for high density memories

3D ICs for high-density memories have significant benefits compared to conventional memories. The first one is high productivity. An area for memory arrays is not required on the semiconductor substrate and the area for the memory control logic can be further reduced for an optimized logic process. Hence, about 4 times more die-per-wafer can be expected for DRAMs with a cell efficiency of about 50%, leading to reduced fab tool investment with increased productivity. Furthermore, the process is optimized for both logic and memory cells because they are processed sequentially. It is well known that processes for logic and memory, especially DRAM and flash, are not compatible. Using 3D ICs, process incompatibility problems are easily solved and SoC (System-on-a-Chip) can be implemented with various embedded memories. An additional advantage is the small form factor. As die sizes shrink for 3D ICs, the yield will increase rapidly, especially important for FPGAs with distributed memories and high-performance CPUs with large cache memories. 3D ICs for high-density memories will extend the lifespan of low-cost CMOS memories.