G. Droulers, S. Ecoffey, M. Guilmain, A. Souifi, M. Pioro-Ladrière, D. Drouin
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In this paper, we show a process for the fabrication of planar sub-attofarad capacitance metal-insulator-metal tunnel junctions with nanometer size. We show the engineering of the material stack, anti-diffusion barrier and electrode metal as well as the result of improved characteristics and stability in time of the devices. This engineering is supported by a simulation tool we developed and its goal is to optimize the original process for the development of high-temperature operating SETs and other innovative nanoelectronic devices.
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