以缺陷为中心的时变性建模与电路仿真的挑战与解决方案

J. Martín-Martínez, J. Diaz-Fortuny, P. Saraza-Canflanca, R. Rodríguez, R. Castro-López, E. Roca, F. Fernández, M. Nafría
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引用次数: 0

摘要

时间相关变异性(TDV)现象严重影响器件和电路的可靠性。为了在电路层面解决TDV的影响,电路设计人员可以使用可靠性感知设计(RAD)工具来实现更可靠的电路。然而,这并不是一项简单的任务,因为RAD工具的开发包括几个步骤,如TDV现象的表征、建模和仿真。此外,在深度缩放的CMOS技术中,TDV显示出随机性,可能使这些步骤复杂化。在这篇受邀的论文中,我们回顾了在开发RAD工具的每个步骤中出现的一些主要挑战,并提供了我们的解决方案。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Challenges and solutions to the defect-centric modeling and circuit simulation of time-dependent variability
Time-Dependent Variability (TDV) phenomena represent a serious concern for device and circuit reliability. To address the TDV impact at circuit level, Reliability-Aware Design (RAD) tools can be used by circuit designers to achieve more reliable circuits. However, this is not a straightforward task, since the development of RAD tools comprises several steps such as the characterization, modeling and simulation of TDV phenomena. Furthermore, in deeply-scaled CMOS technologies, TDV reveals a stochastic nature that can complicate those steps. In this invited paper, we review some of the main challenges that appear in each step of the flow towards the development of RAD tools, providing our solutions to them.
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