全延时可测试顺序电路及其结构最小化问题

A. Matrosova, E. Mitrofanov
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引用次数: 0

摘要

研究了一种基于混合描述电路行为的顺序电路设计方法。研究了顺序电路的组合部分。它的行为用robdd图和单调积的组合来表示。该方法提供了顺序电路的组合部分的完全延迟可测试性。它被定向以减少所获得电路的路径长度。实验结果表明了该方法的优越性。讨论了进一步使电路结构最小化的可能性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Fully delay testable sequential circuits and problem of their structural minimization
The method of a sequential circuit design based on using a mixed description of a circuit behavior is considered. A combinational part of a sequential circuit is examined. Its behavior is represented with a composition of ROBDD-graphs and monotonous products. The method provides fully delay testability of a combinational part of a sequential circuit. It is oriented to cut down the path lengths of the obtained circuits. Experimental results are given that demonstrate advantages of the method. The possibilities of further structural minimization of the circuits are discussed.
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